Method for synthesizing a logic element that implements several functions simultaneously

Abstract

Objectives. The basic element of a field-programmable gate array is a lookup table (LUT). While in canonical normal form LUTs generally implement only one logical function for a given configuration, in this case, there is always an inactive pass transistor element. Moreover, using a single LUT for a single function reduces system-on-a-chip (SoC) scalability. Therefore, the purpose of the present work is to develop a LUT structure for implementing several logic functions simultaneously on inactive transmitting transistors.

Methods. The evolution of LUT structure is presented for three variables, in which the number of simultaneously implemented functions increases. To implement additional functions, the logical device was decomposed with a different number of variables. The structures were modeled in the Multisim electrical simulation system.

Results. The presented simulation of more than two logic functions on inactive parts of the LUT shows the simultaneous operation of two and four logic functions. The complexity for a different number of variables and number of implemented functions is compared.

Conclusions. The simulation results demonstrate the operability of LUT structures in which several logical functions are performed. Thus, when implementing additional functions in the new structure, a smaller number of transmitting transistors is required as compared to a conventional LUT, thus increasing device functionality. The presented solution can be used to increase the number of simultaneously implemented functions of the same variables, which can be important e.g., when implementing code transformations.