Physically unclonable functions in digital integrated circuits

Objectives. Modules that implement physically unclonable functions (PUFs) within a digital chip facilitate the direct use of challenge–response pairs by device applications that can query and read the PUF without external tools or exposing data outside the chip. A PUF can be implemented using technological processes and components already applied in device fabrication. The first of two reviews on PUFs as elements of hardware security infrastructure, the present paper focuses on the formal description of PUFs and designs based on memory modules and timing analysis.

Methods. The following quantitative indicators were applied to formally describe PUFs: computability, uniqueness, feasibility, cloning resistance, and protection against unauthorized access.

Results. PUFs are considered as physical devices with unique signatures. A classification into three PUF groups is proposed: delay-based, memory-based, and analog. Typical examples of the first two groups are outlined. While delay-based solutions provide a large challenge–response space, they require symmetry and/or calibration. In contrast, memory-based PUFs are easier to implement in integrated circuits. With suitable post-processing, they can achieve high reproducibility, making them practical for many applications. Approaches to mitigating voltage and temperature variations are described along with examples of strong memory-oriented PUFs and circuit techniques that enhance resistance to attacks.

Conclusions. PUF-based security technologies demonstrate significant potential, particularly for the Internet of Things. When combined with post-processing and compensation methods, PUFs constitute a mature and effective tool for hardware security.

1. Khalil K., Idris H., Idriss T., Bayoumi M. Lightweight Hardware Security and Physically Unclonable Functions: Improving Security of Constrained IoT Devices. Cham: Springer Nature Switzerland; 2025, 152 р.

2. McGrath T., Bagci I.E., Wang Z.M., Roedig U., Young R.J. A PUF taxonomy. Appl. Phys. Rev. 2019;6(1):011303. https://doi.org/10.1063/1.5079407

3. Zerrouki F., Ouchani S., Bouarfa H. A survey on silicon PUFs. J. Syst. Archit. 2022;127:102514. https://doi.org/10.1016/j.sysarc.2022.102514

4. Alhamarneh R.A., Mahinderjit Singh M. Strengthening Internet of Things Security: Surveying Physical Unclonable Functions for Authentication, Communication Protocols, Challenges, and Applications. Appl. Sci. 2024;14(5):1700. https://doi.org/10.3390/app14051700

5. Tehranipoor M., Pundir N., Vashistha N., Farahmandi F. Hardware Security Primitives. Cham: Springer; 2023, 350 р.

6. Maes R., Verbauwhede I. Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions. In: Sadeghi A.-R., Naccache D. (Eds.). Towards Hardware-Intrinsic Security: Foundations and Practice. Berlin: Springer; 2010. P. 3–37. https://doi.org/10.1007/978-3-642-14452-3_1

7. Suh G.E., Devadas S. Physical Unclonable Functions for Device Authentication and Secret Key Generation. In: Proceedings of the 44th ACM/IEEE Design Automation Conference (DAC 2007), San Diego, CA, USA, June 4–8, 2007. New York: ACM; 2007. P. 9–14. https://doi.org/10.1145/1278480.1278484

8. Lebedev V.R., Pevtsov E.F., Demenkova T.A., Maleto M.I., Filimonov V.V. Method for studying the implementation of Physical Unclonable Function in information systems. Int. J. Open Inf. Technol. 2024;12(1):28–36 (in Russ.). Available from URL: http://injoit.org/index.php/j1/article/view/1712. Accessed July 10, 2025.

9. Gassend B., Clarke D., van Dijk M., Devadas S. Silicon physical random functions. In: Proceedings of the 9th ACM Conference on Computer and Communications Security (CCS 2002), Washington, DC, USA, November 18–22, 2002. New York: ACM; 2002. P. 148–160. https://doi.org/10.1145/586110.586132

10. Vivekraja V., Nazhandali L. Circuit-level techniques for reliable physically unclonable functions. In: Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust (HOST 2009), San Francisco, CA, USA, July 27, 2009. Piscataway, NJ: IEEE; 2009. P. 30–35. https://doi.org/10.1109/HST.2009.5225054

11. Pappu R., Recht B., Taylor J., Gershenfeld N. Physical one-way functions. Science. 2002;297(5589):2026–2030. https://doi.org/10.1126/science.1074376

12. Anandakumar N.N., Hashmi M.S., Tehranipoor M. FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures. Integration. 2021;81:175–194. https://doi.org/10.1016/j.vlsi.2021.06.001

13. Cao Y., Xu J., Wu J., Wu S., Huang Z., Zhang K. Advances in Physical Unclonable Functions Based on New Technologies: A Comprehensive Review. Mathematics (Basel). 2024;12(1):77. https://doi.org/10.3390/math12010077

14. Vatalaro M., De Rose R., Lanuzza M., Crupi F. Weak physically unclonable functions in CMOS technology: A review. Chips. 2025;4(1):3. https://doi.org/10.3390/chips4010003

15. Sklavos N., Chaves R., Di Natale G., Regazzoni F. Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment. Cham: Springer; 2017, 254 р. https://doi.org/10.1007/978-3-319-44318-8

16. Lata K., Cenkeramaddi L.R. FPGA-Based PUF Designs: A comprehensive review and comparative analysis. Cryptography. 2023;7(4):55. https://doi.org/10.3390/cryptography7040055

17. Masoumian S., Selimis G., Wang R., Schrijen G-J., Hamdioui S., Taouil M. Reliability analysis of FinFET-based SRAM PUFs for 16 nm, 14 nm and 7 nm technology nodes. In: Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE 2022), Antwerp, Belgium, March 14–23, 2022. Piscataway, NJ: IEEE; 2022. Р. 1189–1192. https://doi.org/10.23919/DATE54114.2022.9774735

18. Eiroa S., Baturone I., Acosta A.J., Dávila J. Using physical unclonable functions for hardware authentication: A survey. In: Proceedings of the 25th Conference on Design of Circuits and Integrated Systems (DCIS 2010), Lanzarote, Canary Islands, Spain, November 17–19, 2010. Lanzarote; 2010. URL: https://digital.csic.es/bitstream/10261/96029/1/Using%20Physical.pdf

19. Bossuet L., Ngo X.T., Cherif Z., Fischer V. A PUF based on a transient effect ring oscillator and insensitive to locking phenomenon. IEEE Trans. Emerg. Top. Comput. 2014;2(1):30–36. https://doi.org/10.1109/TETC.2013.2287182

20. Brzuska C., Fischlin M., Schröder H., Katzenbeisser S. Physically uncloneable functions in the universal composition framework. In: Rogaway P. (Ed.). Advances in Cryptology – CRYPTO 2011, Santa Barbara, CA, USA, August 14–18, 2011. Book Series: Lecture Notes in Computer Science. Berlin: Springer; 2011. V. 6841. P. 51–70. https://doi.org/10.1007/978-3-642-22792-9_4

21. Tuyls P., Schrijen G-J., Škorić B., van Geloven J., Verhaegh N., Wolters R. Read-proof hardware from protective coatings. In: Goubin L., Matsui M. (Eds.). Cryptographic Hardware and Embedded Systems. CHES 2006, Yokohama, Japan, October 10–13, 2006. Book Series: Lecture Notes in Computer Science. Berlin: Springer; 2006. V. 4249. Р. 369–383. https://doi.org/10.1007/11894063_29

22. Chen Q., Csaba G., Lugli P., Schlichtmann U., Rührmair U. The bistable ring PUF: a new architecture for strong physical unclonable functions. In: Proceedings of the 2011 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2011), San Diego, CA, USA, June 5–6, 2011. Piscataway, NJ: IEEE; 2011. Р. 134–141. https://doi.org/10.1109/HST.2011.5955011

23. Abulibdeh E., Saleh H., Mohammad B., Al-Qutayri M., Veeran A. Area and power efficient implementation of configurable ring oscillator PUF. TechRxiv Preprint; April 2, 2024. https://doi.org/10.36227/techrxiv.171207533.30573247/v1

24. Abulibdeh E., Saleh H., Mohammad B., Al-Qutayri M., Hussain A. Kernel-based response extraction approach for efficient configurable ring oscillator PUF. Sci. Rep. 2025;15:5938. https://doi.org/10.1038/s41598-025-89769-5

25. Ivaniuk A.A., Yarmolik V.N. Configurable ring oscillator with controlled interconnections. Bezopasnost’ informatsionnykh tekhnologii = IT Security (Russia). 2024;31(2):121–133 (in Russ.). https://doi.org/10.26583/bit.2024.2.08

26. Du H., Guo C., Cui S. Optimization design of the RO PUF temperature reliability based on MOSFET temperature characteristics. In: The International Conference Optoelectronic Information and Optical Engineering (OIOE 2024), Wuhan, China, October 18–20, 2024. Proc. SPIE 13513; 2025. Art. 1351324. https://doi.org/10.1117/12.3045630

27. Schaller A., Xiong W., Anagnostopoulos N.A., Saleem M.U., Gabmeyer S., Katzenbeisser S., Szefer J. Intrinsic Rowhammer PUFs: Leveraging the Rowhammer effect for improved security. In: Proceedings of the 2017 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2017), McLean, VA, USA, May 1–5, 2017. Piscataway, NJ: IEEE; 2017. Р. 1–7. https://doi.org/10.1109/HST.2017.7951729

28. Anandakumar N.N., Hashmi M.S., Chaudhary M.A. Implementation of efficient XOR arbiter PUF on FPGA with enhanced uniqueness and security. IEEE Access. 2022;10:129832–129842. https://doi.org/10.1109/ACCESS.2022.3228635

29. Hori Y., Kang H., Katashita T., Satoh A. Pseudo-LFSR PUF: A compact, efficient and reliable physical unclonable function. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig’11), Cancun, Mexico, November 30 – December 2, 2011. Cancun: IEEE; 2011. Р. 223–228. https://doi.org/10.1109/ReConFig.2011.72

30. Marchand C., Bossuet L., Cherkaoui A. Enhanced TERO-PUF implementations and characterization on FPGAs. In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2016), Monterey, CA, USA, February 21–23, 2016. New York: ACM; 2016. Р. 282. https://doi.org/10.1145/2847263.2847298

31. Xu X., Rührmair U., Holcomb D.E., Burleson W.P. Security evaluation and enhancement of bistable ring PUFs. In: Mangard S., Schaumont P. (Eds.). Radio Frequency Identification. RFIDSec 2015. Book Series: Lecture Notes in Computer Science. Cham: Springer; 2015. V. 9440. Р. 3–16. https://doi.org/10.1007/978-3-319-24837-0_1

32. Thirumoorthi M., Jovanovic M., Mirhassani M., Khalid M.A.S. Design and evaluation of a hybrid chaotic-bistable ring PUF. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2021;29(11):1912–1921. https://doi.org/10.1109/TVLSI.2021.3111588

33. Sharifi F., Momeni H., Hosseini A. Ternary bistable ring PUF for high-secure applications. J. Supercomput. 2024;80: 12663–12685. https://doi.org/10.1007/s11227-024-05935-y

34. Rührmair U., van Dijk M. On the practical use of physical unclonable functions in oblivious transfer and bit commitment protocols. J. Cryptogr. Eng. 2013;3(1):17–28. https://doi.org/10.1007/s13389-013-0052-8

35. Rührmair U. Oblivious transfer based on physical unclonable functions. In: Acquisti A., Smith S.W., Sadeghi A.-R. (Eds.). Trust and Trustworthy Computing. TRUST 2010. Berlin: Springer; 2010. V. 6101. Р. 430–440. https://doi.org/10.1007/978-3-642-13869-0_31

36. Roy A., Roy D., Stănică P. On combining Arbiter based PUFs. Cryptogr. Commun. 2025;17(2):493–510. https://doi.org/10.1007/s12095-024-00769-0

37. Driemeyer B., Mandry H., Wiens D.-P., Becker J., Kauffman J.G., Ortmanns M. An eye-opening Arbiter PUF for fingerprint generation using auto-error detection for PVT-robust masking and bit stabilization achieving a BER of 2e-8 in 28 nm CMOS. In: Proceedings of the 2025 IEEE International Solid-State Circuits Conference (ISSCC 2025), San Francisco, CA, USA, February 16–20, 2025. Piscataway, NJ: IEEE; 2025. Р. 300–302. https://doi.org/10.1109/ISSCC49661.2025.10904785

38. Yao Y., Kim M., Li J., Markov I., Koushanfar F. ClockPUF: physical unclonable functions based on clock networks. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), Grenoble, France, March 18–22, 2013. Piscataway, NJ: IEEE; 2013. P. 422–427. https://doi.org/10.7873/DATE.2013.095

39. Khan S., Shah A.P., Chouhan S.S., Roy A., Roy D., Stănică P. Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications. Analog Integr. Circ. Sig. Process. 2020;103:477–492. https://doi.org/10.1007/s10470-020-01642-9

40. Yuan T., Wang P., Zhang Y., Zhou Z. An overclocking clock software PUF circuit with no additional hardware resource overhead based on video coding circuit. Integration. 2025;101:102319. https://doi.org/10.1016/j.vlsi.2024.102319

41. Suzuki D., Shimizu K. The Glitch PUF: a new Delay-PUF architecture exploiting glitch shapes. In: Mangard S., Standaert F.-X. (Eds.). Cryptographic Hardware and Embedded Systems. CHES 2010, August 17–20, 2010. Santa Barbara, CA, USA. Book Series: Lecture Notes in Computer Science. Berlin: Springer; 2010. V. 6225. Р. 366–382. https://doi.org/10.1007/978-3-642-15031-9_25

42. Anderson J. A PUF design for secure FPGA-based embedded systems. In: Proceedings of the 15th Asia South Pacific Design Automation Conference (ASP-DAC 2010), Taipei, Taiwan, January 18–21, 2010. Piscataway, NJ: IEEE; 2010. Р. 1–6. https://doi.org/10.1109/ASPDAC.2010.5419927

43. Ni L., Wang P., Zhang Y., Chen J., Li L., Zhang H. A reliable multi-information entropy glitch PUF using Schmitt trigger sampling method for IoT security. In: 2021 IEEE 14th International Conference on ASIC (ASICON 2021), Kunming, China, October 26–29, 2021. Piscataway, NJ: IEEE; 2021. Р. 1–4. https://doi.org/10.1109/ASICON52560.2021.9620406

44. Nozaki Y., Takemoto S., Yoshikawa M. Error correction method for lightweight cipher PRINCE-based physically unclonable function. In: Proceedings of the 6th International Conference on Information Technology and Computer Communications (ITCC 2024), Xi’an, China, July 5–7, 2024. New York: ACM; 2024. Р. 38–42. https://doi.org/10.1145/3704391.3704397

45. Guajardo J., Kumar S.S., Schrijen G-J., Tuyls P. FPGA intrinsic PUFs and their use for IP protection. In: Paillier P., Verbauwhede I. (Eds.). Cryptographic Hardware and Embedded Systems – CHES 2007, Vienna, Austria, September 10–13, 2007. Lecture Notes in Computer Science. Berlin: Springer; 2007. V. 4727. Р. 63–80. https://doi.org/10.1007/978-3-540-74735-2_5

46. Holcomb D.E., Burleson W.P., Fu K. Initial SRAM state as a fingerprint and source of true random numbers for RFID tags. Proceedings of the Conference on RFID Security. 2007;7(2):01–012.

47. Gebali F., Mamun M. Review of physically unclonable functions (PUFs): Structures, models, and algorithms. Front. Sens. 2022;2:751748. https://doi.org/10.3389/fsens.2021.751748

48. Holcomb D.E., Burleson W.P., Fu K. Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comput. 2009;58(9):1198–1210. https://doi.org/10.1109/TC.2008.212

49. Kumar S., Guajardo J., Maes R., Schrijen G-J., Tuyls P. The butterfly PUF: protecting IP on every FPGA. In: Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust (HOST 2008), Anaheim, CA, USA, June 3–4, 2008. Piscataway, NJ: IEEE; 2008. Р. 67–70. https://doi.org/10.1109/HST.2008.4559053

50. Farha F., Ning H., Ali K., Chen L., Nugent C. SRAM-PUF-based entities authentication scheme for resource-constrained IoT devices. IEEE Internet Things J. 2021;8(7):5904–5913. https://doi.org/10.1109/JIOT.2020.3032518

51. Su Y., Holleman J., Otis B. A 1.6 μJ/bit stable chip-ID generating circuit using process variations. In: Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC 2007), San Francisco, CA, USA, February 11–15, 2007. Piscataway, NJ: IEEE; 2007. Р. 606–611. https://doi.org/10.1109/ISSCC.2007.373466

52. Tehranipoor F., Karimian N., Yan W., Chandy J.A. Investigation of DRAM PUFs reliability under device accelerated aging effects. In: Proceedings of the 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD, USA, May 28–31, 2017. Piscataway, NJ: IEEE; 2017. Р. 1–4. https://doi.org/10.1109/ISCAS.2017.8050629

53. Yue M., Karimian N., Yan W., Anagnostopoulos N.A., Tehranipoor F. DRAM-based authentication using deep convolutional neural networks. IEEE Consum. Electron. Mag. 2021;10(4):8–17. https://doi.org/10.1109/MCE.2020.3002528

54. Sutar S., Raha A., Raghunathan V. D-PUF: an intrinsically reconfigurable DRAM PUF for device authentication in embedded systems. In: Proceedings of the 2016 International Conference on Compilers, Architectures and Synthesis of Embedded Systems (CASES 2016), Pittsburgh, PA, USA, October 2–7, 2016. New York: ACM; 2016. Р. 1–10. https://doi.org/10.1145/2968455.2968519

55. Chew Y.Y., Lim W.L., Tan J.L., Ooi C.Y. In-depth review and comparative analysis of DRAM-based PUFs. IEEE Access. 2025;13:79367–79384. https://doi.org/10.1109/ACCESS.2025.3566068

56. Wilson T., Cambou B. Tamper-sensitive pre-formed ReRAM-based PUFs: Methods and experimental validation. Front. Nanotechnol. 2022;4:1055545. https://doi.org/10.3389/fnano.2022.1055545

57. Napolean A., Sivamangai N.M., Sharon N., Naveen Kuma R. Review on resistive random access memory based physical unclonable function circuits for high security. Procedia Environ. Sci. Eng. Manag. 2023;10(1):41–52. URL: http://www.procedia-esem.eu/pdf/issues/2023/no1/5_Napolean_22.pdf. Дата обращения 10.07.2025. / Accessed July 10, 2025.

58. Adel M.J., Rezayati M.H., Moaiyeri M.H., et al. A robust deep learning attack immune MRAM-based physical unclonable function. Sci. Rep. 2024;14:20649. https://doi.org/10.1038/s41598-024-71730-7

59. Go S.X., Wang Q., Lim K.G., Lee T.H., Bajalovic N., Loke D.K. Ultrafast near-ideal phase-change memristive physical unclonable functions driven by amorphous state variations. Adv. Sci. (Weinh.) 2022;9(36):e2204453. https://doi.org/10.1002/advs.202204453

60. Yang J., Lei D., Chen D., Li J., Jiang H., Luo Q., et al. Machine-learning-resistant 3D PUF with 8-layer stacking vertical RRAM and 0.014% bit error rate using in-cell stabilization scheme for IoT security applications. In: 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 12–18, 2020. Piscataway, NJ: IEEE; 2020. Р. 28.6.1–28.6.4. https://doi.org/10.1109/IEDM13553.2020.9372107

61. Li J., Cui Y., Gu C., Wang C., Liu W., Kvatinsky S. A highly reliable dual-mode RRAM PUF with key concealment scheme. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 2025. https://doi.org/10.1109/TCAD.2025.3536376