Application of double-error correction codes to protect configuration programmable logic memory against space radiation
https://doi.org/10.32362/2500-316X-2023-11-5-54-62
Abstract
Objectives. Programmable logic integrated circuits of the field programmable gate array (FPGA) type based on static configuration memory are widely used in the electronics of onboard spacecraft systems. Under the influence of space radiation, errors may occur in the FPGA configuration memory. The main methods of protection against such errors involve various options for reservation triggers, as well as the use of error-correcting codes in special error detection and correction circuits. The purpose of the present work is to determine which error-correcting codes are best suited to the implementation of internal scrubbing of the FPGA configuration memory taking redundancy into account.
Methods. The paper analyses various methods for scrubbing FPGA configuration memory, which are used to correct errors caused by the action of space radiation. It is proposed to increase the efficiency of internal scrubbing of the FPGA configuration memory using codes that correct both single- and double-adjacent SEC-DED-DAEC errors. In this case, the need to perform external scrubbing of the configuration memory is reduced by overwriting it with a reference configuration from non-volatile radiation-resistant memory; in this way, FPGA downtime caused by the external scrubbing procedure is reduced. Due to the known SEC-DED-DAEC codes having a non-zero probability of erroneous detection and subsequent erroneous correction of a double non-adjacent error, as well as various redundancy and implementation complexities, a study was made of the most efficient code for internal scrubbing.
Results. The results showed that the Datta, Neale and Hoyoon–Yongsurk codes are optimal from the indicated positions. Recommendations are given for selecting a specific code depending on the specific requirements for a particular planned space mission.
Conclusions. The study confirms the effectiveness of protecting the memory of programmable logic by using two-error-correcting codes.
About the Authors
E. S. LepeshkinaRussian Federation
Ekaterina S. Lepeshkina, Assistant, Information Technology Security Department; Engineer, “Small Satellite” Laboratory
31, Krasnoyarsky Rabochy pr., Krasnoyarsk, 660037
Scopus Author ID 57218577296
Competing Interests:
The authors declare no conflicts of interest.
N. D. Kustov
Russian Federation
Nikita D. Kustov, Assistant, Information Technology Security Department; Engineer, “Small Satellite” Laboratory
31, Krasnoyarsky Rabochy pr., Krasnoyarsk, 660037
Scopus Author ID 57218577358
Competing Interests:
The authors declare no conflicts of interest.
V. K. Khanov
Russian Federation
Vladislav Kh. Khanov, Cand. Sci. (Eng.), Associate Professor, Information Technology Security Department; Head of the “Small Satellite” Laboratory
31, Krasnoyarsky Rabochy pr., Krasnoyarsk, 660037
Scopus Author ID 56491191500
Competing Interests:
The authors declare no conflicts of interest.
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- The study aimed to determine which error-correcting codes are best suited to the implementation of internal scrubbing of the FPGA configuration memory taking redundancy into account.
- The results showed that the Datta, Neale, and Hoyoon–Yongsurk codes are optimal from the indicated positions. Recommendations are given for selecting a specific code depending on the specific requirements for a particular planned space mission.
- The study confirms the effectiveness of protecting the memory of programmable logic by using two-error-correcting codes.
Review
For citations:
Lepeshkina E.S., Kustov N.D., Khanov V.K. Application of double-error correction codes to protect configuration programmable logic memory against space radiation. Russian Technological Journal. 2023;11(5):54-62. https://doi.org/10.32362/2500-316X-2023-11-5-54-62