mireabulletinRussian Technological JournalRussian Technological Journal2782-32102500-316XRTU MIREA10.32362/2500-316X-2026-14-2-29-41XHLRAXmireabulletin-1463Research ArticleИНФОРМАЦИОННЫЕ СИСТЕМЫ. ИНФОРМАТИКА. ПРОБЛЕМЫ ИНФОРМАЦИОННОЙ БЕЗОПАСНОСТИINFORMATION SYSTEMS. COMPUTER SCIENCES. ISSUES OF INFORMATION SECURITYО проектировании гетерогенных вычислительных систем с аппаратным ускорением массово-параллельной потоковой обработки данныхHeterogeneous computing systems with hardware acceleration of massively parallel stream processing designhttps://orcid.org/0000-0002-1797-7585ЗуевА. С.ZuevA. S.

Зуев Андрей Сергеевич, к.т.н., доцент, заведующий кафедрой квантовых информационных технологий, практической и прикладной информатики

119454, Москва, пр-т Вернадского, д. 78

Andrey S. Zuev, Cand. Sci. (Eng.), Associate Professor, Head of the Department of Quantum Information Technologies, Practical and Applied Informatics, Institute of Information Technologies

zuev_a@mirea.ruhttps://orcid.org/0000-0002-1039-2429СоветовП. Н.SovietovP. N.

Советов Петр Николаевич, к.т.н., доцент, кафедра корпоративных информационных систем, Институт информационных технологий

119454, Москва, пр-т Вернадского, д. 78.

Peter N. Sovietov, Cand. Sci. (Eng.), Associated Professor, Department of Corporate Information Systems, Institute of Information Technologies

peter.sovietov@gmail.comhttps://orcid.org/0000-0001-6456-4794ТарасовИ. Е.TarasovI. E.

Тарасов Илья Евгеньевич, д.т.н., доцент, профессор кафедры корпоративных информационных систем, Институт информационных технологи

119454, Россия, Москва, пр-т Вернадского, д. 78

Ilya E. Tarasov, Dr. Sci. (Eng.), Associated Professor, Professor, Department of Corporate Information Systems, Institute of Information Technologies

tarasov_i@mirea.ruМИРЭА – Российский технологический университетРоссияMIREA – Russian Technological UniversityRussian Federation2026090420261422941Copyright © Зуев А.С., Советов П.Н., Тарасов И.Е., 20262026Зуев А.С., Советов П.Н., Тарасов И.Е.Zuev A.S., Sovietov P.N., Tarasov I.E.This work is licensed under a Creative Commons Attribution 4.0 License.https://www.rtj-mirea.ru/jour/article/view/1463Цели

Цели. Необходимость ускорения вычислений и достижения высоких показателей энергоэффективности приводит к расширению сфер использования специализированных гетерогенных вычислительных систем, имеющих в своем составе аппаратные ускорители с массовым параллелизмом вычислений. Целью настоящей работы является создание методики анализа и оценки вариантов реализации аппаратных ускорителей для задач массово-параллельной потоковой обработки данных, отражающей все направления совершенствования характеристик применяемых аппаратных ускорителей.

Методы

Методы. Использованы методы проектирования и моделирования цифровых систем.

Результаты

Результаты. Предложен метод сравнительной оценки эффективности архитектуры гетерогенной вычислительной системы на основе аппаратных ускорителей с массовым параллелизмом вычислений, выполняемых независимо программируемыми узлами. Введен коэффициент ускорения вычислений, объединяющий три направления совершенствования характеристик применяемых аппаратных ускорителей – математическое обеспечение и микроархитектура, инструментарий проектирования, технологии изготовления (литография). Предложена основанная на решении оптимизационной задачи методика анализа и оценки вариантов реализации применяемых аппаратных ускорителей.

Выводы

Выводы. Полученные авторами формулы расчета коэффициента ускорения вычислений и пропускной способности совокупности аппаратных ускорителей учитывают многоканальную и поблочную массово-параллельную обработку потоков данных. В отличие от известных подходов к поиску архитектурных решений, предлагаемая оценка вариантов реализации аппаратных ускорителей может быть проведена на самых ранних этапах проектирования с учетом версий алгоритма и альтернатив их реализации, влияющих на оптимизацию аппаратной архитектуры. Предложенная методика анализа и оценки вариантов реализации аппаратных ускорителей может применяться при разработке технических заданий на их изготовление, при их проектировании в соответствии с заданными требованиями, для обоснования решений относительно их конфигурации, а также при составлении заданий на научно-исследовательские и опытно-конструкторские работы с целью достижения целевых значений характеристик для конкретных задач массово-параллельной потоковой обработки данных и функциональных возможностей систем автоматизированного проектирования

Objectives

Objectives. The growing demand for higher computational performance and energy efficiency has motivated the increasing adoption of specialized heterogeneous computing systems incorporating hardware accelerators with massive parallelism. This paper aims to develop a methodology for the analysis and evaluation of hardware accelerator implementation strategies for large-scale parallel stream data processing which systematically captures all major directions of performance improvement.

Methods

Methods. The study employs established techniques of digital system design and modeling.

Results

Results. A comparative evaluation method is introduced to assess the efficiency of heterogeneous computing architectures based on massively parallel hardware accelerators composed of independently programmable nodes. A computational acceleration ratio is defined which consolidates three key dimensions of accelerator improvement: algorithmic support and microarchitecture; design automation tools; and fabrication technologies (lithography). Furthermore, the study proposes an optimization-based methodology for the systematic analysis and evaluation of the alternatives for hardware accelerator implementation.

Conclusions

Conclusions. The expressions derived herein for calculating the computational acceleration ratio and the aggregate throughput of hardware accelerators account for both multichannel and block-based massively parallel data stream processing. In contrast to conventional architectural exploration approaches, the evaluation method proposed herein enables hardware accelerator design alternatives to be assessed at the earliest stages of the design cycle. This incorporates variations in algorithmic versions and implementation strategies which influence hardware architecture optimization. The proposed methodology for analyzing and evaluating implementation options for hardware accelerators can be used to develop technical specifications for their manufacture, design them according to specified requirements, and justify configuration decisions. It can also support research and development assignments to achieve target characteristics for certain domain-specific tasks of massively parallel stream data processing and CAD capabilities.

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The authors declare that there are no conflicts of interest present.